The present invention relates generally to a duty cycle correction device, and more particularly to static compensation of an active clock edge shift for a duty cycle correction circuit.
Designing digital circuits requires a clear design of signal timing and the right sequence of signals dependent from each other. Special focus is often on investigating timing behavior, especially, on waveforms of critical signals, like clock signals. In complex chip designs, clock signals often run across multiple clock trees and clock meshes to different physical areas of a semiconductor die. In particular, rising and falling edges of signals require special attention. Getting this timing behavior of these critical signals of integrated circuits right is paramount for the functionality and reliability of VLSI (very large-scale integrated circuit) chips. Besides the signal waveform in general, the duty cycle is a relevant figure of merit and has to be monitored and potentially adapted for meeting design requirements. For the duty cycle of signals, in particular clock signals, only a small variability may be acceptable. The clock signal(s) may be deformed by running through the clock trees and clock meshes. Thus, a “re-establishment” of the predefined duty cycle may be required.
To correct or change the duty cycle of signals, DCC (duty cycle correction) circuits are used. Typical DCC circuits receive an input signal as well as a configuration or control signal defining the desired duty cycle characteristics, in particular, the percentage of time the signal has the logical value “0” as well as the percentage of time the signal has the logical value of “1” within one cycle. In an ideal case, the DCC moves only the inactive clock edge of the signal or clock signal. However, due to the limitations of real electronic circuits which do not behave like ideal circuits, it appears that both edges, active and inactive, may be impacted.